For a processor to read a piece of compressed data corresponding to a desired piece of non-compressed data from a memory such as ROM storing a plurality of pieces of compressed data, a technology disclosed for example in Patent Literature 1 is known.
According to the technology disclosed in Patent Literature 1, a processor uses an address translation table to read a variable-length program code that is compressed from a desired program code.
The address translation table stores a pair of address values for each program code. One of the address values in a pair is to be used by the processor to read the program code, and the other indicates a memory location at which a corresponding compressed program code is stored.
That is, according to the technology disclosed in Patent Literature 1, the address value to be used for reading a desired program code is acquired from a processor and translated with the use of an address translation table. In this way, a compressed program code corresponding to the desired program code is read from the memory location indicated by the translated address value.